Software Implementation vs. Hardware Implementation: The Avionic Test System Case-Study

International audienceThis paper presents a development methodology that helps designers to map efficiently applications onto a heterogeneous CPU/FPGA system. An industrial case study is presented and aims at meeting performance and real-time requirements with the help of our architecture capabilities and avionic model parallelization. Different avionic model implementations will be presented in order to explain how to find the best trade-off between performance and design-time

Virtual Platform for Embedded System Power Estimation

International audienceIn this paper, we propose a virtual platform for power estimation of processor based embedded systems. Our platform consists of a combination of Functional Level Power Analysis (FLPA) for power modeling and fast system prototyping for transactional simulation. In this proposal, we aim at esti- mating power automatically with the help of power models and SystemC IP libraries. These libraries are enriched with different power models and various hardware components required by the embedded platforms. This will allow to use our proposed virtual platform to port various hardware systems and applications in the same environment in order to satisfy the requirements of reliable and efficient design space exploration. Our experiments performed on this virtual embedded platform show that the obtained power estimation results are less than 3% of error in an average for all the processor when compared to the real board measurements

Correct and Energy-Efficient Design of a Multimedia Application on SoCs

This report presents the design and analysis of multimedia applications such as the JPEG encoder on multiprocessor architectures. A model-based approach is adopted by using the UML Marte specifications. An abstract clock analysis is proposed to deal with the correctness of system behaviors and to find the most suitable execution platform configurations regarding performance and energy consumption. We claim that our approach offers a rapid and reliable design space analysis, which is crucial when implementing complex systems.Ce rapport présente la conception et l'analyse d'applications multimédia telles qu'un encodeur JPEG sur une architecture multiprocesseur. Une approche basée sur des modèles est adoptée en considérant des spécifications en UML Marte. Une analyse reposant sur des horloges abstraites est proposée afin d'aborder la correction des comportements d'un système, et trouver les configurations les plus adéquates pour son exécution, du point de vue de la performance et de la consommation d'énergie. Notre approche permet une analyse rapide et fiable de l'espace de conception ; cela est crucial pour l'implantation des systèmes complexes

An Efficient Power Estimation Methodology for Complex RISC Processor-based Platforms

International audienceIn this contribution, we propose an efficient power estima- tion methodology for complex RISC processor-based plat- forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu- ate accurately the activities used in the related power mod- els. The combination of the two parts above leads to a het- erogeneous power estimation that gives a better trade-off be- tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench- marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained power estimation results pro- vide less than 3% of error for ARM940T processor, 3.5% for ARM CortexA8 processor-based system and 1x faster compared to the state-of-the-art power estimation tools

An MDE Approach for Energy Consumption Estimation in MPSoC Design

International audienceEnergy Consumption is a leading criterion to take into ac- count in the design of multiprocessor systems on chip (MP- SoC). In this paper, we present a solution to estimate the energy consumption early inMPSoC design in order to nd a good performance/energy trade-o in the design ow. This solution is based on the injection of consumption estimators between the hardware components during the co-simulation of a system at the CABA (Cycle Accurate Bit Accurate) level. These estimators are designed using a design frame- work and the corresponding SystemC code is automatically generated thanks to a model driven approach. Our solution oers an energy estimation framework without changing the IP(Intellectual Property)source codes, using standalone es- timation modules, which allows their reuse. The accuracy of this approach is checked by integrating the consumption estimation in the simulation of signicant applications

System-Level Power Estimation Methodology for MPSoC based Platforms

Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dès les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final.Shifting the design entry point up to the system-level is the most important countermeasure adopted to manage the increasing complexity of Multiprocessor System on Chip (MPSoC). The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of power and energy efficiency. However, taking decisions at this level is very difficult, since the design space is extremely wide and it has so far been mostly a manual activity. Efficient system-level power estimation tools are therefore necessary to enable proper Design Space Exploration (DSE) based on power/energy and timing.VALENCIENNES-Bib. électronique (596069901) / SudocSudocFranceF

A Model Driven Design Framework for High Performance Embedded Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. High performance embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of high performance embedded systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performances; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations. This paper presents the Gaspard design framework for high performance embedded systems as a solution to the above issues. Gaspard uses the repetitive Model of Computation (MoC), which offers a powerful expression of the parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities, Gaspard allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high level specifications of high performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application

Gaspard2 UML profile documentation

This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit the usage of control flow on those applications. In addition to those notions, the profile contains a package introducing factorization mechanisms to enable the compact description of massively parallel and repetitive systems

Dynamic reconfiguration and low power design : towards self-adaptive massively parallel embedded systems

Sophisticated embedded systems are becoming wide spread today in aerospace, automotive, avionic, and defence industries. They are responsible for control, collision avoidance, driver assistance, target tracking, navigation and communications, amongst other functions. According to the characteristics of these functionalities, high computation rates should be well-delivered while carrying-out intensive signal processing. Furthermore, these embedded systems often operate in uncertain environments. So, they should adapt their functioning mode according to the environmental conditions to provide reliability, fault tolerance, deterministic timing guarantees, and energy efficiency. Undoubtedly, the essential feature of systems to reconfigure themselves (at the hardware or the software level) at run-time comes with additional complexity in the different design flow steps.The design of these sophisticated embedded systems calls for several teams with different domain experts covering electronics, architecture, software engineering, etc. We are in a new era promoting for the dynamicity of heterogeneous and parallel processing. Academic and industrial researchers must address the challenges inherent from this new trend at all the design steps. The scope of my research topics covers mainly low-power design methodology, dynamic execution models for heterogeneous and massively parallel architectures, and reconfiguration model for next generation 3D-FPGAs. My research promotes the convergence towards self-adaptive massively parallel embedded systems

Multiprocessor system-on-chip modeling and simulation : performance and energy consumption estimation

La simulation des systèmes embarqués multiprocesseurs (MPSoC), dés les premières phases de conception, joue un rôle primordial puisqu'elle permet de réduire le temps d'arrivée sur le marché du produit final. Néanmoins, comme ces MPSoC deviennent de plus en plus complexes et hétérogènes, les méthodes conventionnelles de simulation de bas niveau ne sont plus adéquates. La solution proposée à travers cette thèse est l'intégration dans un seul environnement de plusieurs niveaux de simulation. Ceci permet l'évaluation des performances à un niveau précoce dans le flot de conception. L'environnement est utile dans l'exploration de l'espace des solutions architecturales et permet de converger rapidement vers le couple Architecture/Application le plus adéquat. Dans la première partie de cette thèse, nous présentons un outil de simulation performant et qui offre, à travers les trois niveaux qui le composent, différents compromis entre la vitesse de simulation et la précision de l'estimation des performances. Ces trois niveaux se différencient par les détails de l'architecture nécessaires à chacun et se basent sur le standard SystemC-TLM. Dans la deuxième étape, nous nous sommes intéressés à la consommation d'énergie dans les MPSoc. Pour cela, nous avons enrichi notre environnement de simulation par des modèles de consommation d'énergie flexibles et précis. Enfin dans la troisième étape de notre thèse, une chaîne de compilation basée sur la méthodologie Ingénierie Dirigée par les Modèles (!DM) est développée et intégrée à l'environnement Gaspard. Cette chaîne permet la génération automatique du code SystemC à partir d'une modélisation de haut niveau d'un MPSoc.Multiprocessor system on chip (MPSoC) simulation in the first design steps has an important impact in reducing the time to market of the final product. However, MPSoC have become more and more complex and heterogeneous. Consequently, traditional approaches for system simulation at lower levels cannot adequately Support the complexity needed for the design of future MPSoc. ln this thesis, we propose a framework composed of several simulation levels. This enables early performance evaluation in the design flow. The proposed framework is useful for design space exploration and permits to find rapidly the most adequate Architecture/Application configuration. ln the first part ofthis thesis, we present an efficient simulation tool composed of three levels that offer several performance/energy tradeoffs. The three levels are differentiated by the accuracy of architectural descriptions based on the SystemC- TLM standard. ln the second part, we are interested by the MPSoC energy consumption. For this, we enhanced Our simulation framework with flexible and accurate energy consumption models. FinaIly in the third part, a compilation chain based on a Model Driven Engineering (MDE) approach is developed and integrated in the Gaspard environment. This chain allows automatic SystemC code generation from high level MPSoC modeling